In this article, the authors present a novel approach to designing SoC (System-on-Chip) architectures for deep neural networks (DNNs). The goal is to find a balance between latency, power consumption, and area of the SoC. The authors use a Pareto optimal set approach, which involves optimizing multiple objective functions simultaneously.
The article starts by defining several key concepts
- Definition 1: A design point x in the SoC architecture design space X is denoted as a combination of features listed in TABLE I.
- Definition 2: Multi-objective optimization of SoC is defined to find x ∈ X that trades off multiple objective functions, including latency, power consumption, and area.
- Definition 3: The Pareto optimal set is a set of design points that cannot be improved in one objective function without worsening at least one other objective function.
The authors then describe their proposed approach to SoC architecture design, which involves using a simplified model to evaluate the performance of various DNNs on different SoC architectures. They use importance-based pruning and initialization to reduce the number of design points that need to be evaluated, while still ensuring that the most representative points are included in the evaluation.
The authors then present their experimental results, which demonstrate the effectiveness of their approach in finding a Pareto optimal set of SoC architectures that balance latency, power consumption, and area for various DNNs. They also show that their approach can significantly reduce the number of design points that need to be evaluated while still providing accurate results.
Finally, the authors conclude by highlighting the importance of their work in demystifying the SoC architecture design process for DNNs and providing a practical framework for finding a Pareto optimal set of SoC architectures. They also suggest several directions for future research, including exploring new optimization techniques and integrating additional design constraints.
In summary, this article presents a novel approach to SoC architecture design for DNNs that leverages multi-objective optimization and importance-based pruning to find a Pareto optimal set of architectures that balance latency, power consumption, and area. The authors demonstrate the effectiveness of their approach through experimental results and highlight its potential to significantly reduce the number of design points that need to be evaluated while still providing accurate results.
